Node-on-a-chip

The practical applications of wireless sensor network require the sensor nodes to be high in calculating ability, low in power consumption, small in size, as well as cheap in cost. Nowadays, most of the sensor nodes are developed based on the general-purpose embedded platforms using commercial off-the-shelf electronic components . Depends on the design of the specific software, these general-purpose sensor nodes can be adjusted to meet various application requirements. Thus the design flexibility is one of the main advantages. However, the disadvantages of them are revealed as big in size and relatively low in calculating ability and efficiency, especially when there are complicated signal processing algorithms or protocols under processing. Besides, the hardware architecture of the embedded sensor nodes cannot support the “Sleep–Event wake up” mechanism because when the sensor is waiting for an event, the CPU may be awake for event detecting and couldn't fall asleep, which will waste a lot of power.

To improve those issues above, we propose the system architecture and design methodology of a sensor network node-on-a-chip, called EasiSOC, based on hardware and software co-design and System on Chip (SOC) technology. The unique features of the EasiSOC include: (1) a processor and co-processor cooperation system architecture is designed with specific functional hardware modules developed to improve the signal collection, processing, and networking functionalities; ( 2 ) an efficient ultra low-power management mechanism, called “Sleep–Events wakeup”, is developed to enable the node to work in an appropriate operating mode depending on its working status and the power levels required; and ( 3 ) a data protection mechanism is proposed to guarantee the embedded program data against being read out after the data download process completed to improve the security of the system.

Accomplishments

We have presented the design, implementation, and evaluation of the prototype sensor node based on a FPGA platform as well as the node-on-a-chip development effort. The proposed node can meet most of the wireless sensor network application requirements. The power cost of the node’s digital circuit can be reduced to about 14%.

Xi Huang, Ze Zhao and Li Cui. EasiSOC: Towards Cheaper and Smaller, Mobile Ad-hoc and Sensor Networks 2005(MSN'05), LNCS 3794，229-238，2005.

Future Directions

After the successful performance verification, we converted the FPGA design into an ASIC. The node-on-a-chip design has been completed and it is going through the tape-out procedure at the moment. In the future, we will evaluate the performance of the ASIC, and improve the architecture and modules to the evaluation result. Moreover, we also consider adding the base band module and the RF transceiver module to the ASIC design in order to reduce the size of the sensor node.